CVE-2024-42279: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

Severity: medium (CVSS 5.5 v3.1)
Exploited in the wild: not listed in CISA KEV
EPSS: 0.2% probability of exploitation in the next 30 days
Public exploit or detection template: none known
Published: 2024-08-17 · updated 2026-10-30

Description

In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

Affected products

Linux kernel: from 6.0 before 6.6.44; from 6.7 before 6.10.3 — fixed in 6.6.44, 6.10.3
Linux: 6.0 — fixed in 6.11

How to fix

Upgrade to a fixed version: Linux kernel 6.6.44, 6.10.3; Linux 6.11. Check the vendor advisory for mitigations.

References

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