CVE-2026-23554: Use after free of paging structures in EPT

Severity: high (CVSS 7.8 v3.1)
Exploited in the wild: not listed in CISA KEV
EPSS: 0.1% probability of exploitation in the next 30 days
Public exploit or detection template: none known
Published: 2026-03-23 · updated 2026-06-17
Weakness: CWE-367

Description

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

Affected products

xen: from 4.17

References

https://xenbits.xenproject.org/xsa/advisory-480.html
http://www.openwall.com/lists/oss-security/2026/03/17/6
http://xenbits.xen.org/xsa/advisory-480.html

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