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CVE-2026-29643

• Severity: high (CVSS 7.1 v3.1)
• Exploited in the wild: not listed in CISA KEV
• EPSS: 0.2% probability of exploitation in the next 30 days
• Public exploit or detection template: none known
• Published: 2026-04-20 · updated 2026-06-17
• Weakness: CWE-703

Description

XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.

References

• https://docs.riscv.org/reference/isa/priv/machine.html
• https://docs.riscv.org/reference/isa/priv/priv-csrs.html
• https://github.com/OpenXiangShan/XiangShan/issues/3959
• https://github.com/OpenXiangShan/XiangShan/pull/3966
• https://github.com/OpenXiangShan/XiangShan/issues/3959

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